FIG. 1 shows a cross section side view of a prior art T-gate structure. A T-gate structure 100 often has a T-shaped gate 125, referred to as simply a T-gate. In general a T-gate is any device which has a narrow gate foot 65 and a relatively wider gate head 165. Sometimes the same or similar structures are referred to as Y-gates and/or mushroom gates due to their final shape. In yet another instance, a gamma-gate or asymetric gate can be produced. A gamma-gate has a cross section similar to the Greek letter gamma. Accordingly, the terms T-gate, Y-gate, mushroom gate, gamma-gate, and asymmetric gate refer to a tiered gate structure with a narrow gate foot 65 and a relatively wider gate head 165. In this disclosure the term T-gate, the most general and widely used term to refer to such tiered gate structure devices, is intended to encompass all of these structural variations.
Most T-gate processes utilize electron beam lithography to produce short gate length devices. While gate lengths less than 100 nanometers are commonly achievable, the short height of the gate foot 65 (the distance between the surface of the substrate 110 and the bottom of the gate head 165) required to produce such short gate lengths, creates unwanted parasitics between the gate head 165 and the source 120, and between the gate head 165 and the drain 130, indicated as Cgs and Cgd, respectively. This occurs because of the aspect ratio limitation between feature size and resist thickness in electron beam lithography. Electrons undergo forward and back scattering during exposure which limit the minimum feature size to around half of the resist thickness at a 50 kV acceleration voltage. This short separation also hinders nitride coverage of the gate structure 125 during passivation.
FIG. 1 also illustrates the voids 167 and 168 which form during metal evaporation. Voids 167 and 168 form on either side of the gate foot 65 extending upward between the gate foot 65 and gate head 165. This can present a reliability problem. The upward extending voids 167 and 168 form during metal evaporation when some metal coats the side of the imaging layer mask causing the metal to self-mask. As the evaporation continues, the voids 167 and 168 form between the gate foot 65 and gate head 165 until gate foot 65 and gate head 165 finally join, which may occur well into the gate head 165. In some cases, the gate head 165 can fail to join with the gate foot 65 during fabrication, thereby forming non-functioning devices. In its connection with gate head 165, the gate foot 65 extends into and attaches to the gate head 165 recessed within voids 167 and 168. This causes a weakness in the gate structure 125 where cracks can propagate and cause breakage of the gate structure 125.
Furthermore, a downward extending recess 169 is present in the top of the gate head 165 because the gate foot 65 is formed in the same metallization step as the gate head 165. Thus, as the deposited metallization layer extends to the substrate 110 to form the gate foot 65, it leaves the recess 169 in the gate head 165 located above the gate foot 65. Any cracks forming from the upwardly extending voids 167 and 168 need only extend to the downwardly extending recess 169 to cause breakage of the gate head 165 from the gate foot 65.
Another disadvantage of the T-gate structure of FIG. 1 is that the gate length (width of the gate foot 65 adjacent the substrate 110) can not be measured during a conventional fabrication process. For example, with the process of U.S. Pat. No. 6,417,084, by Singh, et al., entitled T-GATE FORMATION USING A MODIFIED CONVENTIONAL POLY PROCESS, issued Jul. 9, 2002, herein incorporated by reference, the undercut regions are located beneath a wider contact portion which obscures measurement of the gate length. In U.S. Pat. No. 6,387,783, by Furukawa, et al., entitled METHODS OF T-GATE FABRICATON USING A HYBRID RESIST, issued May 14, 2002, herein incorporated by reference, the wider top 117 as well as layer 111 prevents measurement of the gate length during fabrication. In these processes, the gate length is measured by destroying the T-gate device.
Also, traditional methods are performed with two exposure passes. In the first exposure, the top resist is exposed to define the gate head 165. The lower resist which will define the gate foot 65, is partially exposed in the first exposure, but not enough to develop it. The top resist is developed and a second exposure is used to define the gate foot 65. This creates a history on the lower resist layer. This history can cause non-uniformities in the gate foot 65 to occur across the wafer.
What is needed is a non-destructive way to determine gate length. Furthermore, what is needed is a process that allows measurement of the gate length in situ during processing. Also, what is needed is a simple process that improves process uniformity and yields. In addition, what is needed is a process that allows reducing of the gate to source capacitance and the gate to drain capacitance.